1. Field of the Invention
The present invention relates to pseudo-LSI (Large Scale Integration) devices for use in developing LSI circuits, and to debugging systems having the pseudo-LSI device incorporated therein. The debugging system incorporating the pseudo-LSI device will hereinafter be referred to as an "emulation system".
2. Description of the Related Art
To develop LSI devices in a shortened period of time with an improved efficiency, it has been proposed in recent years to prepare a pseudo-LSI device by an emulation system before the fabrication of an LSI device and to connect the pseudo-LSI device to a target device (actual device) to confirm the operation of the hardware.
When the operation of the hardware is confirmed to some extent, the firmware is checked concurrently for the confirmation of its operation. When the operation of the firmware has been confirmed completely, the operation of the software is confirmed, and the overall system is tested for evaluation. Accordingly, it is desired to use a plurality of pseudo-LSI devices or emulation systems.
The construction of a conventional emulation system will be described with reference to the block diagram of FIG. 16.
The conventional emulation system 1j comprises an operation unit 2j and a pseudo-LSI device 3j.
The operation unit 2j comprises an MPU (microprocessor unit), R/W controller, memory, etc. for downloading circuit data (net list) forwarded form an unillustrated host computer or the like onto the pseudo-LSI device 3j.
The pseudo-LSI device 3j has an FPGA (Field Programmable Gate Array) 12' corresponding in the number of gates to the scale of the pseudo-LSI device. The FPGA 12' has, for example, an SRAM (Static Random Access Memory) incorporated therein. Writing circuit data onto the SRAM provides a pseudo-LSI having a specific hard circuit. Accordingly, the circuit data downloaded from the operation unit 2j is written to the SRAM to provide a corresponding pseudo-LSI device. When the device 3j has a plurality of FPGAs 12', an address decoder or the like is provided as required.
The pseudo-LSI device 3j downloaded with the circuit data is connected to various target devices (target boards) 7, checked for the operation of the hardware of the device 3j itself and operated to test, debug and evaluate the target devices 7.
The FPGA 12' is proposed to evaluate a designed internal circuit of VLSI chip, ASIC device or the like nearly in the form of an actual device, internally has a large quantity of programmable gate structure and is therefore adapted to evaluate the designed circuit nearly as an actual device when programmed with the circuit.
With advances in semiconductor techniques in recent years, however, VLSI chips and ASIC devices having an internal circuits with an increased number of gates are made available in larger quantities, giving rise to the necessity of using a plurality of FPGAs for emulating the function of such large-scale circuits. For the use of a plurality of FPGAs, the assignment of input and output pins of the individual FPGAs needs to be determined, and the connection patterns for connecting the FPGAs must be prepared on a printed circuit board before use.
Nevertheless, different circuits to be evaluated by the pseudo-LSI device require different programs for the FPGA constituting the pseudo-LSI device and different interface signals for communication between the FPGAs. Accordingly, every time a particular internal circuit is to be evaluated, there arises a need to determine input-output pin assignments and to prepare connection patterns on the board. Use of the pseudo-LSI device thus constructed fails to utilize to any extent the universal feature that FPGAs are programmable, necessitating much labor and a great cost for preparing the connection patterns for the evaluation of each of different circuits.
U.S. Pat. No 5,109,353 issued on Apr. 28, 1992 discloses a technique wherein FPGAs are connected to one another by predetermined fixed patterns and are wired according to the internal programs of the respective FPGAs. Although the determination of input-output pin assignments is conventionally followed by the preparation of connection patterns, the proposed technique conversely employs the fixed connection patterns for interconnecting the FPGAs, which are programmed in conformity with the connection patterns.
FIG. 17 is a diagram showing an embodiment of this technique. FPGAs 101, 102, 103, 104 are interconnected by many connection patterns. In the case where the system of this structure is to provide a logic circuit for delivering from a terminal 43 the logical product of signals input to terminals 41, 42, the FPGA 101 is programmed with a pattern 71 through which the signal input from the terminal 41 is delivered as it is to a connection pattern 44, and the FPGAs 102, 103 are similarly programmed respectively with a pattern 72 for connecting the pattern 44 to a connection pattern 45 and with a pattern 73 for connecting the terminal 42 to a connection pattern 46.
The FPGA 104 is programmed with an AND circuit 74 for calculating the logical product of the signals from the connection patterns 45, 46 and is so programmed as to deliver the output of the circuit from the terminal 43. Programming the FPGAs 101, 102, 103, 104 in this way makes it possible to provide a logic circuit for the input signals to the terminals 41, 42 to give a logical product at the terminal 43 even with use of the fixed connection patterns.
VLSI chips or ASIC devices generally provide internal circuits wherein completed specified circuits are integrated in combination into a single chip, and are capable of constituting simplified circuits wherein such component circuits are integrated to ensure connection therebetween or compensate for a delay of signals through the component circuits, thus making it possible to use high-frequency clock signals and realizing a high-speed operation and integration of circuits. However, with the structure disclosed in the foregoing publication U.S. Pat. No. 5,109,353, great importance is given only to the universal usefulness thereof, so that there is a very great likelihood for the FPGAs to be connected to one another, to connectors or to external devices via other internal wiring of the FPGAs. If the internal wiring of the FPGAs is used for these connections, the input-output buffer of the FPGAs having the internal wiring for the connections will cause a delay in signal transmission, which entails operation errors of the circuit provided. This gives rise to a need to additionally use a circuit for compensating for the delay in signal transmission although such a circuit need not be added to the actual circuit concerned. It is then difficult to evaluate the test circuit under the same conditions as the actual circuit.
Further although no problem arises if signal transmission necessitating a high speed is effected only between adjacent FPGAs, actual circuits are rarely so designed. If it is attempted to provide such an arrangement intentionally, the circuit concerned, which is complex, needs then be reconstructed through a procedure involving nearly the same difficulty as is encountered in constructing the whole circuit from the beginning. For this reason, some signals are transmitted through many FPGAs, so that it is difficult to conduct emulation without using an additional circuit for compensating for a delay of signals.
Additionally, VLSI chips or ASIC devices, which comprise completed specified circuits in combination, are likely to have wiring for bidirectional signal transmission between circuits. If other internal wiring of FPGA is used for the connection, there arises a need for a signal for a change-over between the input and output of input-output buffer of the FPGA, consequently necessitating connection of signal lines and also a complex control circuit.
The conventional pseudo-LSI device 3j shown in FIG. 16 has another problem in that when separated from the operation unit 2j, the device fails to function as such because the circuit data written onto the FPGA 12' disappears.
Accordingly, the pseudo-LSI device 3j is usable only as connected to the operation unit 2j and can not be separated from the unit 2j for use in confirming the operation of the device 3j and testing and debugging the target device.
Therefore, when the pseudo-LSI device 3j as completely checked for operation is to be used for testing in the next other section, not only the device 3j but also the operation unit 2j must be moved at the same time, and the circuit data thereafter needs to be downloaded from the operation unit 2j onto the device 3j again.
Moreover, in the case where tests and the like in different stages of developing LSI devices are to be carried out concurrently in different sections, emulation systems 1j, not less than the number of these sections in number, are necessary to result in an enormous equipment cost.